1. Field of the Invention
This invention relates to a structure of a semiconductor device, and more particularly, to a dual damascene structure of a semiconductor device.
2. Description of the Related Art
As the integration of an integrated circuit (IC) increases, the number of interconnections used in an IC increases accordingly. In order to design a layout containing an increased number of interconnections, a layout that contains more than two metal layers has become a popular method for fabricating a semiconductor IC. Since the increased integration of an IC makes it more difficult to meet the requirements of the yield and reliability of interconnections, newer methods and structures have been developed and applied in the semiconductor fabrication process. The formation of a dual damascene includes forming trenches on dielectric layers, and then filling the trenches with metal, such as copper, that is difficult to pattern by an etching process. Because a dual damascene structure satisfies the requirement of low resistance and high electromigration, it has been widely used in the fabrication process of 0.25-.mu.m or smaller very large scale integration (VLSI) devices for obtaining an efficient and reliable interconnection.
FIGS. 1A through 1C are schematic, cross-sectional views showing the formation process of a conventional dual damascene.
Referring to FIG. 1A, a first dielectric layer 30 is formed on a substrate 10 by a deposition process, such as a plasma enhanced chemical vapor deposition (PECVD) process. The substrate 10 already contains conducting regions 20 such as source/drain regions. Then, a patterned silicon nitride 50 is formed on the dielectric layer 30, wherein the patterned silicon nitride layer 50 contains openings 40 that expose a portion of the dielectric layer 30. The positions of the openings 40 respectively correspond to the positions of the conducting regions 20 underneath. A second dielectric layer 60 is next to be formed on the patterned silicon nitride layer 50.
Referring to FIG. 1B, an etching process is performed on the first dielectric layer 30 and the second dielectric layer 60 by using the silicon nitride layer 50 as a mask for the first dielectric layer 30 and the conducting regions 20 as an etching stop layer. A number of first via holes 70, which expose the conducting regions 20, and a number of second via holes 80, which are located above the silicon nitride layer 50, are formed by the foregoing etching process, wherein the etching process includes a dry etching process.
After that, with reference to FIG. 1C, a metal layer, such as copper, silver, aluminum, aluminum-silver alloy, or aluminum-copper alloy, is deposited on the second dielectric layer 60, and fills the first via holes 70 and the second via holes 80. Then, by performing a process such as an etching back process or a chemical mechanical polishing process, any portion of the deposited metal that is located on the top surface of the second dielectric layer 60 is removed to form a metal layer 90.
Generally, the first dielectric layer 30 and the second dielectric layer 60 include a high-permittivity material such as silicon dioxide or silicon nitride, which is an excellent heat transfer material. However, a high-permittivity material implies a large capacity, which worsens resistance-capacitance (RC) delay, This in turn slows down the operation of the semiconductor device and degrades the performance of the semiconductor device.